My apologies -- this has been covered here: viewtopic.php?p=35723&hilit=multi+part#p35723
The wrap-up was that even in 2024 that multipart and heirarchy blocks are incompatible. Still an open issue about whether it might be added/improved in V5 or beyond.

I will remove my similar question, but has this situation changed in V5 ? Note that some multiparts are just the symmetrical parts, but some include a non-similar part (like the power connections for the opamps, etc) so the solution could be quite difficult, parsing out the divide-by-x parts ...

I would like to lay out a block of circuitry using a subset of a multi-part component (example: two out of four logic gates). I don't see how to do this. It seems that if I add U1 to the block, using U1.1 and U1.2, then each new block instantiated would generate a new component rather than drawing ...

For anyone who gets here: for at least DT4 and later, you can open each of the libraries in the library configuration tool and change where they each point... to correct their target location to the new location. I changed these library pointers and didn't appear to need the Environment Variables to ...

I've changed the name and location of a NAS, then decided on still another location I want my board files and libraries to be a part of.

In the past I know there was a lot of exporting, text editing, and importing just to fix these issues. Does the newer Library Setup and Environment Variables ...

The process of outputting gerbers, sometimes many times over the life of a changing project, is time-consuming and any improvement in its operation would be helpful. When projects increase in size, sometimes the rendering of a layer can take minutes, so the ability to output these project Gerbers ...

Looking for the same thing, and also worked great for me.

Thanks Tom

Sorry I should have been more clear. This is DRC, in the layout package.

The errors are that the gap is smaller than the net-based clearance established everywhere else. This is what I was saying before: I've set specific higher voltage clearance limits expecting DRC to do what it's designed to do ...

I use a driver meant to operate at high voltage, which increases creepage/clearance between the HV contacts by interleaving structural contacts that are not connected internally at all.

Like this:
Pin 1 (HV) Pin 2 (NC) Pin 3 (HV) Pin 4 (NC) Pin 5 (HV)

Diptrace shows a DRC failure between all ...

Isn't it true that this updating of all libraries to add default additional fields (as TomG showed) is only valid for user libraries? Aren't all the standard libraries protected against writing or updating?

This would leave some of the libraries more difficult to use.

Do I have that right?