Search found 59 matches
- 03 Jan 2024, 10:42
- Forum: DipTrace Schematic Capture
- Topic: Multi-part components
- Replies: 7
- Views: 2127
Re: Multi-part components
So, how do you make full use of a "multi-part" component when the different parts are used in different circuits that are drawn on different pages ?
- 30 Dec 2023, 09:59
- Forum: DipTrace Schematic Capture
- Topic: Multi-part components
- Replies: 7
- Views: 2127
Re: Multi-part components
What is the proper way to spread the different parts of a multi-part component across several pages ?
- 30 Dec 2023, 09:58
- Forum: DipTrace Schematic Capture
- Topic: Multi-part components
- Replies: 7
- Views: 2127
Multi-part components
What is the proper way to spread the different parts of a multi-part component across several pages ?
- 27 Sep 2022, 16:31
- Forum: DipTrace PCB Layout
- Topic: Exporting a BOM for a Panelized PCB
- Replies: 1
- Views: 1587
Re: Exporting a BOM for a Panelized PCB
My mistake !
Sorry for the bother.
Andre
Sorry for the bother.
Andre
- 26 Sep 2022, 00:16
- Forum: DipTrace PCB Layout
- Topic: Exporting a BOM for a Panelized PCB
- Replies: 1
- Views: 1587
Exporting a BOM for a Panelized PCB
I have tried the latest version of Diptrace but my problem remains. When I export the PnP file for the Panelized PCB, everything seems in order; cordinates for the 4x4 matrix of PCB's. However, when I export the BOM file for the same Panelized PCB, (4x4 matrix), the resulting Exported file is for on...
- 03 Jul 2022, 03:26
- Forum: DipTrace PCB Layout
- Topic: Errors generated by Vias joining a Top and Bottom heatsink plate.
- Replies: 8
- Views: 3500
Re: Errors generated by Vias joining a Top and Bottom heatsink plate.
Thanks again Tom !
May you enjoy Summer.
Andre
May you enjoy Summer.
Andre
- 02 Jul 2022, 19:54
- Forum: DipTrace PCB Layout
- Topic: Errors generated by Vias joining a Top and Bottom heatsink plate.
- Replies: 8
- Views: 3500
Re: Errors generated by Vias joining a Top and Bottom heatsink plate.
Yes, you are correct. The plates were added to the signal layers; top and bottom. I did assign all of the vias to the appropiate Net, a rather tedious job. However, I was unable to assign the plates to the Net. I could not find a command to do so. Can you explain HOW ? Also, maybe you can suggest a ...
- 28 Jun 2022, 21:18
- Forum: DipTrace PCB Layout
- Topic: Errors generated by Vias joining a Top and Bottom heatsink plate.
- Replies: 8
- Views: 3500
Re: Errors generated by Vias joining a Top and Bottom heatsink plate.
No, they are not "copper poured".
They were created with the "drawing tool" and assigned to the different layers.
They were created with the "drawing tool" and assigned to the different layers.
- 28 Jun 2022, 00:26
- Forum: DipTrace PCB Layout
- Topic: Errors generated by Vias joining a Top and Bottom heatsink plate.
- Replies: 8
- Views: 3500
Errors generated by Vias joining a Top and Bottom heatsink plate.
I'm sure that I must be doing something wrong, but I can't figure out what. When I attach a "Top" layer based heatsink plate to a "Bottom" layer heatsink plate, by using static Vias; I get a small red circle error for each of the Vias, inspite of attaching to the proper NEts, bot...
- 10 Jun 2022, 12:59
- Forum: Other questions and issues
- Topic: Schematic Worksheet
- Replies: 1
- Views: 2397
Re: Schematic Worksheet
Found it in sheet settings