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- 27 Aug 2017, 19:43
- Forum: Basic Schematic and PCB Design
- Topic: Problem related to Ratelines and Nets
- Replies: 4
- Views: 6739
Hi, I came across a problem where I'm unable to set hierarchy of nets, it leads me to unwanted messed up ratlines in PCB design application. Scenario is like this I have an IC U1 and two headers J1 and J2. All patterns has 4 pins each. In Schematic design, I first connected U1 pins to J1 pins (pins...