Search found 13 matches

by kjrowett
13 Dec 2019, 03:29
Forum: DipTrace PCB Layout
Topic: component overlap not flagged
Replies: 2
Views: 1078

Re: component overlap not flagged

Thanks, again Tom.
by kjrowett
12 Dec 2019, 21:31
Forum: DipTrace PCB Layout
Topic: component overlap not flagged
Replies: 2
Views: 1078

component overlap not flagged

DT PCB let me place a 0402 resistor "underneath" a 64 pin TQFP package - i.e. both components were on the same layer.

Is there a way for DRC to detect this?

KR
by kjrowett
27 Nov 2019, 17:49
Forum: Bug reports
Topic: Copper pour clearance issues
Replies: 12
Views: 4760

Re: Copper pour clearance issues

Tom - thanks... A colleague just pointed out there are actually two copper pours, with the boundary right where the error is occurring. Both copper pours are in the same net - GND, and have the same priority. That has to cause the pour fill algorithm some issues. Why did I design the copper pours th...
by kjrowett
26 Nov 2019, 18:48
Forum: Bug reports
Topic: Copper pour clearance issues
Replies: 12
Views: 4760

Re: Copper pour clearance issues

Relay is Panasonic AGQ200A12Z. Thanks. We've used this part in several other designs w/o issue, with copper pours. The bottom silk is an interesting item to try. I've moved the via and the relay, slightly. It changes where the error is.

KR
by kjrowett
26 Nov 2019, 14:34
Forum: Bug reports
Topic: Copper pour clearance issues
Replies: 12
Views: 4760

Re: Copper pour clearance issues

reposting, as last post didn't show up...

I can't post the design file.

What's notable is the copper pour worked correctly for five of the six pads of the relay, and many, many vias. I did look at the net class, and the rules.
by kjrowett
26 Nov 2019, 12:31
Forum: Bug reports
Topic: Copper pour clearance issues
Replies: 12
Views: 4760

Re: Copper pour clearance issues

Pad K1:1 - Copper pour (gap=6.2mil; Rule= 7mil) (The rule violation is SMD to Copper clearance)
StaticVia142 - Copper pour (gap=6.16 mil; Rule = 7 mil) (rule violation is Via to Copper)
by kjrowett
25 Nov 2019, 19:38
Forum: Bug reports
Topic: Copper pour clearance issues
Replies: 12
Views: 4760

Re: Copper pour clearance issues

Nothing telling. Seems correct.
by kjrowett
25 Nov 2019, 17:15
Forum: Bug reports
Topic: Copper pour clearance issues
Replies: 12
Views: 4760

Copper pour clearance issues

I've added a component with long rectangular pads (the component is a Panasonic SMD relay). I also added two via. After updating the copper pour, I get clearance issues on one of the SMD pads and on one of the Vias. Looking at the copper pour, it's not uniform on each side of the relay, and the side...
by kjrowett
08 Oct 2019, 14:46
Forum: Feature requests
Topic: MacOS 10.15 Catalina Support
Replies: 8
Views: 4713

Re: MacOS 10.15 Catalina Support

I'd also like to get an update when a release will be available for Catalina. Apple released OSX Catalina today - it will be hard to not upgrade.
by kjrowett
22 Jul 2019, 13:05
Forum: DipTrace PCB Layout
Topic: pad is locked, but doesn't show in right click menu
Replies: 1
Views: 671

pad is locked, but doesn't show in right click menu

HI, I have a PAD I wish to delete. I right click and select delete. I get an error dialog box, noting the pad is locked. When I select the pad and right click on it, the lock/unlock item isn't present. Any ideas? The pad essentially became un-connected as part of the QFN package that I deleted (bein...