About the #3 behavior on the tartan' list above : the pours of the same priority left unchanged by DT showing the short connection - error. This makes sense because what could be the logic to give a preference to one or another if both have the same priority? Indeed DT should insist on the PCB ...

Very useful demonstration - thank you. Shows how the highest priority pour is the "underdog" getting the remains of the allocated space on PCB.
Somebody who decided to coded it this way was at that moment very angry at his Boss ... revenge :)) I can understand, I experienced such moments too :)

So lower priority pours are the first to take space on the board and the higher priority pours take of whatever space remains between already allocated pours and traces? This indeed confirms what I observed - the clearance requirement of the higher priority pour is ignored in favor of the lower ...

I am having the same problem all the time when making a pour. Priority '0' is the highest according to the manual. No matter how I play with clearances of the adjacent pours - the lowest clearance seem to always prevail. What is definite though that setting highest priority pour to a larger ...

I got repeatedly into this kind of difficulty which I see as the only troublesome lack in DT ... even though this is a "feature" but it feels more like a problem when spending more than hour to find a work around to a somewhat usual task in PCB development.
The same feature is required when ...

I found that during the assembly I still need to have DT loaded for many reasons - for BOM references, for pads corrections for the next version... and turning on and off the layers to see what I need to see ... so assembly view just one click away...
The end result - DT rocks but only those can ...

Question to Tom:
What would we do without you?:)
Thank you very much

PS I chose to go with your "PS" option: uncover all vias

Thanks a lot Tom - it's all clear about filled rectangular to keep out mask.
As a side issue (but important) we all need to keep out mask from jumper vias to allow soldering jumper wire directly to the copper. Ideally it would be best if via style could be optionally marked to keep out mask for ...

Hello, I need to keep out mask layer to allow exposed copper area on the bottom layer for cooling a component above (top layer) through a perforated pad. I drew a rectangular and placed it on the bottom mask layer. When I chose bottom mask layer to be displayed, I can see this rectangular (no other ...

It would be nice to know that somebody from DT developers have read this post and thought it over. I spent hours analyzing and experimenting with this topic before I came up with this suggestion hoping to help to make DT even better.