DipTrace 4.2 Release

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matttay
Posts: 62
Joined: 07 Aug 2010, 18:58

Re: DipTrace 4.2 Release

#11 Post by matttay » 10 Nov 2021, 09:31

Hi DipTrace folks....do you have any hints on how to use this feature in 4.2: - Submenu for creating pattern internal pad-to-pad connection (avoid accidental creation).

I can not find any reference to this in the help or the application. This seems useful for creating a shorted resistor part. Thanks!

Alex
Technical Support
Posts: 3897
Joined: 13 Jun 2010, 23:43

Re: DipTrace 4.2 Release

#12 Post by Alex » 11 Nov 2021, 01:12

matttay wrote: 10 Nov 2021, 09:31 Hi DipTrace folks....do you have any hints on how to use this feature in 4.2: - Submenu for creating pattern internal pad-to-pad connection (avoid accidental creation).

I can not find any reference to this in the help or the application. This seems useful for creating a shorted resistor part. Thanks!
When you attach a pattern to a component, you can click on a pad and drag a ratline to another pad. Now popup hint appears that allows you either connect two pads or cancel the action.

matttay
Posts: 62
Joined: 07 Aug 2010, 18:58

Re: DipTrace 4.2 Release

#13 Post by matttay » 11 Nov 2021, 07:08

Thanks for the info.

In the schematic below, R2 is a shorted resistor, where pads 1 and 2 are connected as you've described. Note that Net0 and Net 4 are distinct and not merged (this makes sense)
schematic.png
schematic.png (12.1 KiB) Viewed 2021 times
In the layout below, net 4 is now gone, and merged with net 0. So, the schematic has a net 4, but the layout does not. That seems odd. You can also see the implicit connection between the pads on R2. That makes sense. But, verification passes, even though there is no connection between the two. If I route the connection between the pads on R2, net connectivity still passes.
Layout.png
Layout.png (7.34 KiB) Viewed 2021 times
So, I guess there are two weird things with this feature that I hope you could explain:

1) Why are net names merged on the layout and not the schematic? I think the schematic is the correct behavior. I think the net names should NOT be merged in layout. Plus, when the nets exist in the schematic but not in the layout, that seems dangerous.
2) If you connect the pins when attaching the pattern to the component, that seems to suggest a copper connection is expected at some point. That makes sense. And thus, a missing connection as shown above (no copper between R2 pads) should be "check net connectivity" error. However, the "check net connectivity" is happy if the R2 pads are connected or not. That seems a bug. And that bug is related to the merging of nets noted in 1)

Thanks!

Alex
Technical Support
Posts: 3897
Joined: 13 Jun 2010, 23:43

Re: DipTrace 4.2 Release

#14 Post by Alex » 12 Nov 2021, 03:10

1. Nets are merged at the stage of converting schematic to PCB. We think merging nets in Schematic is not good idea. For example, if nets were merged in schematic and you replaced the resistor with internal connection to a resistor without internal connection you wouldn't restore initial nets. Also think about hierarchical schematic and related layout, nets are different on them due to the nature of hierarchy.
2. There is no connectivity error because resistor's pins are internally connected. The software thinks the connection is implemented through the resistor once you solder it on the board.

AZot
Posts: 1
Joined: 15 Sep 2020, 20:47

Re: DipTrace 4.2 Release

#15 Post by AZot » 13 Nov 2021, 15:11

novarm44 wrote: 04 Nov 2021, 01:55 The instruction how to make DipTrace portable:
https://diptrace.com/docs/diptrace_portable.pdf
Mistake in item 2 - "...rename it to DipTrace_Portable." Need rename to Data_Portable.

jgerhardy
Posts: 20
Joined: 22 Oct 2017, 20:20

Checksums - Re: DipTrace 4.2 Release

#16 Post by jgerhardy » 16 Nov 2021, 04:20

Hello DipTrace-Team,

Thank you guys for the new update.

I have downloaded -DipTrace 4.2 Trial 64-Bit for Windows,
but I have not found any checksum on on the web page.

Where can I find the checksums for the file downloads?

Greetings,
John

Alex
Technical Support
Posts: 3897
Joined: 13 Jun 2010, 23:43

Re: Checksums - Re: DipTrace 4.2 Release

#17 Post by Alex » 17 Nov 2021, 00:51

jgerhardy wrote: 16 Nov 2021, 04:20 Hello DipTrace-Team,

Thank you guys for the new update.

I have downloaded -DipTrace 4.2 Trial 64-Bit for Windows,
but I have not found any checksum on on the web page.

Where can I find the checksums for the file downloads?

Greetings,
John
Here are md5 checksums of DipTrace 4.2.0.0:
9a254880d8b5ded889fa45f0ee434919 dipfree_en.exe
4b4f536ca147e95191feba6310866d39 dipfree_en64.exe
54b1982a04246661f304360c2e7eb294 diptrace_en.exe
8c4d19b02e2db303c5972207576e8926 diptrace_en64.exe
b96e224b2f94c28cf6fa15c18bc68d24 DipTrace.dmg

matttay
Posts: 62
Joined: 07 Aug 2010, 18:58

Re: Checksums - Re: DipTrace 4.2 Release

#18 Post by matttay » 17 Nov 2021, 08:25

jgerhardy wrote: 16 Nov 2021, 04:20 Where can I find the checksums for the file downloads?
Better than checksums is the digital signature. Right click on the downloaded EXE and select the "digital signature" tab. There you will see the signature list and the name of the signer. Click on "details" and you will see a message if the signature is correct or not. If a single byte in the EXE has changed, its digital signature will fail. And if you try to run an exe that has been tampered with, you will see a warning that it's not signed. it's awesome that the apps are signed.

matttay
Posts: 62
Joined: 07 Aug 2010, 18:58

Re: DipTrace 4.2 Release

#19 Post by matttay » 17 Nov 2021, 08:29

Alex wrote: 12 Nov 2021, 03:10 1. Nets are merged at the stage of converting schematic to PCB. We think merging nets in Schematic is not good idea. For example, if nets were merged in schematic and you replaced the resistor with internal connection to a resistor without internal connection you wouldn't restore initial nets. Also think about hierarchical schematic and related layout, nets are different on them due to the nature of hierarchy.
2. There is no connectivity error because resistor's pins are internally connected. The software thinks the connection is implemented through the resistor once you solder it on the board.
What is the purpose of this feature then? I don't understand how this would be used. Normally if you have a part that has several pins shorted together, you just make extra pins on the part symbol and then connect them all together on the schematic, it's not a big deal.

Are there other features where the netlist between the schematic and pcb isn't the same?

Also a way is needed to enable a jumper that is by default connected, but can be cut with an xacto during development so that a current sense resistor can be added. This is a very basic part of all product development and it's not possible to do in diptrace without warnings. How do you suggest this is accomplished?

Alex
Technical Support
Posts: 3897
Joined: 13 Jun 2010, 23:43

Re: DipTrace 4.2 Release

#20 Post by Alex » 18 Nov 2021, 00:55

matttay wrote: 17 Nov 2021, 08:29
Alex wrote: 12 Nov 2021, 03:10 1. Nets are merged at the stage of converting schematic to PCB. We think merging nets in Schematic is not good idea. For example, if nets were merged in schematic and you replaced the resistor with internal connection to a resistor without internal connection you wouldn't restore initial nets. Also think about hierarchical schematic and related layout, nets are different on them due to the nature of hierarchy.
2. There is no connectivity error because resistor's pins are internally connected. The software thinks the connection is implemented through the resistor once you solder it on the board.
What is the purpose of this feature then? I don't understand how this would be used. Normally if you have a part that has several pins shorted together, you just make extra pins on the part symbol and then connect them all together on the schematic, it's not a big deal.

Are there other features where the netlist between the schematic and pcb isn't the same?

Also a way is needed to enable a jumper that is by default connected, but can be cut with an xacto during development so that a current sense resistor can be added. This is a very basic part of all product development and it's not possible to do in diptrace without warnings. How do you suggest this is accomplished?
There are components with internally connected pads. For example, transistors in TO-263 package or most tact switches. It's good to have neat schematic without extra pins and control what pads to connect (either or all) in PCB Layout.
You can ignore connectivity error if you are sure a short circuit between different nets is wanted. We will consider a way to do it without warnings.

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