Keeping testpoint our of BOM

Drawing Schematics, Hierarchical Design, BOM, Exporting net-lists, etc.
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jgerhardy
Posts: 9
Joined: 23 Oct 2017, 03:20

Keeping testpoint our of BOM

#1 Post by jgerhardy » 15 May 2018, 07:08

Hello,

the testpoint included in the standard libraries also shows up in the BOM
even thought it is not really a part, at least not for SMD pads.

How can I keep the testpoint out of the BOM?

Regards,
John

Tomg
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Joined: 20 Jun 2015, 14:39

Re: Keeping testpoint our of BOM

#2 Post by Tomg » 15 May 2018, 08:02

"...How can I keep the testpoint out of the BOM?..."
Since its Part Type is "Normal", you can't. If you create a custom test point component and set its Part Type to "Net Port", it will be excluded from the BOM.
Tom

jgerhardy
Posts: 9
Joined: 23 Oct 2017, 03:20

Re: Keeping testpoint out of BOM

#3 Post by jgerhardy » 15 May 2018, 09:05

Hello Tomg,

Thanks for your response. I gave it a try and it does keep the part out
of the BOM. Joy! :) They look great when I replaced the testpoints
already in the schematic with the new "net port" testpoints.

However, when I add a new "net port" testpoint into the schematic. It seems
now that the RefDes "TP" which I put in the component editor is discarded
and replaced with "Net Port" (see picture) :(

Is there is a way to change the "NetPort" back to "TP"?

Regards,
John
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Tomg
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Re: Keeping testpoint our of BOM

#4 Post by Tomg » 15 May 2018, 09:39

1) In the Schematic Editor, right-click on the component and select Properties... in the pop-up menu to bring up the Component Properties dialog window.
2) In the Component Properties dialog window click on the [Markings] tab, choose which markings to show and then select OK.

p.s. When running the PCB Layout editor's 3D Preview tool a window will appear to warn you that there is no STEP file for the SMD test point. You can choose to ignore the annoying warning or you can attach a blank STEP file to the pattern using the Pattern Editor to get rid of the warning. Don't forget to forward-propagate any changes.
Tom

jgerhardy
Posts: 9
Joined: 23 Oct 2017, 03:20

Re: Keeping testpoint our of BOM

#5 Post by jgerhardy » 15 May 2018, 10:50

Hello tomg,

Thanks for the suggestion. I looked into the markings but
the component does not have a "TP" anymore.
180515_tp_schem.jpg
In schematic the RefDef of the component has "NetPort" in it, even
thought it has "TP" in the RefDes in the component editor.
180515_tp_comp.jpg
Am I missing something here?

Thanks also for the tip with the STEP file. Is there a perhaps a blank STEP
file in the 3D library or do I need to generate one?

Regards,
John
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Tomg
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Joined: 20 Jun 2015, 14:39

Re: Keeping testpoint our of BOM

#6 Post by Tomg » 15 May 2018, 11:36

"...I looked into the markings but the component does not have a "TP" anymore..."
If updating the component from the library didn't help, I guess you'll have to change the RefDes manually using the Component Properties dialog window.

WARNING
I almost forgot one important caveat about using Netports in DipTrace (Aargh! In my opinion, this is a major bug in the program!): Netports with the same name will automatically connect to each other, so before connecting another copy of the same Netport to a different net, change its NAME or an unreported connection/merge with the other Netport's net will be created. Naturally, once the Netport name is changed the Update From Library tool will no longer be able to find the new name in the source library in case you need to update the component. There are ways around that, of course, but it can be a pain in the posterior to remember everything.

Hmmm. Maybe this wasn't such a good idea after all?

However, as long as you don't forget about this DipTrace Netport behavior and are willing to accept the risk of any negative consequences in the event of a "rushed" Netport placement, soldier on.

"...Is there a perhaps a blank STEP file in the 3D library or do I need to generate one?..."
As far as I know, you'll need to generate one. Just open a new PCB file devoid of any and all objects, run 3D Preview (it should be blank) and save it as a STEP file.
Tom

jgerhardy
Posts: 9
Joined: 23 Oct 2017, 03:20

Re: Keeping testpoint our of BOM

#7 Post by jgerhardy » 16 May 2018, 06:06

Hello tomg,

Ok. Thanks much for your time and effort in pursuing this.
Even with the help and tutorial, there are always a lot of
questions unanswered so your explanations, e.g. about
the net port feature of DT is a great help which I appreciat
alot ( I am sure others, too). I'll put the question into
support and see what they say.

Creating the STEP in PCB works great! Kudos for the tip.
I don't have so much experience in 3D-Modelling, so this is a
new adventure for me. When I exported the blank STEP file
there is a choice of "solid (recommended)" and "parts."
Unfortunately, the help does not help much here. Can you
tell me what the difference is?

Regards,
John

Tomg
Expert
Posts: 1409
Joined: 20 Jun 2015, 14:39

Re: Keeping testpoint our of BOM

#8 Post by Tomg » 16 May 2018, 08:29

Hi John,
I really don't know what the difference is between the Solid and Parts options. It's possible that it has something to do with the exported file's size, but I can't be sure. Experience tells me that some parts won't be properly rendered during export when using the Solid option, especially if they overhang the PCB edge (e.g. the shaft of a potentiometer). If that happens, using the Parts export option will usually solve the problem.

Another quirk to watch out for is holes not being rendered when viewing the PCB in some 3D CAD applications (e.g. Alibre Design or Solid Space). Surprisingly, this problem can be solved by drawing the Board Outline in a counter-clockwise direction before using the 3D Preview tool to generate the STEP file. When the Board Outline has been drawn in a clockwise direction the holes will not render properly. It's my belief that there is a bug in the DipTrace STEP file generator since this hole-rendering oddity can be seen in at least two different external programs.
Tom

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