BUS Confusion

Drawing Schematics, Hierarchical Design, BOM, Exporting net-lists, etc.
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TPE_PCB
Posts: 1
Joined: 27 Oct 2013, 04:58

BUS Confusion

#1 Post by TPE_PCB » 27 Oct 2013, 05:05

I have two distinct buses. I have a signal named SPI_CS in the first bus. I'd like to add a different signal named SPI_CS in the second bus. I get a warning that "net with such name already exists outside the bus" and it doesn't allow it to be added.

This doesn't make sense. Why does the schematic require that every single bus name is different even across buses? Every bus should be able to have its own version of a signal name. That is why you have buses!

Am I misunderstanding something? Will this be changed in upcoming version?

Alex
Technical Support
Posts: 3125
Joined: 14 Jun 2010, 06:43

Re: BUS Confusion

#2 Post by Alex » 28 Oct 2013, 08:04

DipTrace doesn't allow different nets with the same name even though they are in different busses. Give different names for the nets. This logic was taken in the beginning therefore we can't change it. Otherwise the same files would work in different way in current and future versions.

matttay
Posts: 41
Joined: 08 Aug 2010, 01:58

Re: BUS Confusion

#3 Post by matttay » 03 Nov 2013, 14:27

This is really unfortunate. There should be a switch someplace to preserve back compat. But if the user has no interest in preserving back compat, then they should have the most powerful means available for helping to manage complexity.

A hierarchical bus structure, where BusA.Clock is different from BusB.Clock is pretty standard in all PCB packages and higher level description languages.

Complex designs today can have dozens of clocks, a half dozen spi buses, etc. It's very difficult for the user to manage all these different names for different signals in his head. That is what tools are for.

Brent
Posts: 14
Joined: 07 May 2012, 02:59

Re: BUS Confusion

#4 Post by Brent » 30 May 2019, 21:03

These are good points.

Was this ever implemented?

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