Stiching Layers together with Vias

Making PCB Layouts, Manual routing, Auto-routing, Copper pouring, Updating from Schematic, Manufacturing Output
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matttay
Posts: 62
Joined: 07 Aug 2010, 18:58

Stiching Layers together with Vias

#1 Post by matttay » 04 May 2016, 08:42

There is a basic requirement to stitch ground layers together on PCBs, but there seems confusion on the forum. Additionally:

1) The stitch via must survive re-pours (because there are a lot of these vias)
2) Must not generate a DRC error (because there are a lot of these vias)

How can diptrace do this most basic function?

If I place a static via 2 into an area that is ground plane on every layer (tied to the same ground), the default is that I get a DRC error and the via doesn't survive the repour (I get 4 DRC errors per via).

I then specify "hide via ring in layer" which gets rid of two errors. But then resulting via doesn't survive repours.

I then select Thermal Settings-> Use Custom (Whole via, Connect: Yes) and I get a via that survive repours.

But I'm still stuck with a DRC error Copper pour-Drill Gap, where the gap is negative.

How can I make a static via that survive re-pours and doesn't generate a DRC????

Thanks!

Jiisuki
Posts: 12
Joined: 27 Apr 2014, 11:33

Re: Stiching Layers together with Vias

#2 Post by Jiisuki » 04 May 2016, 09:14

Try connecting the vias to the pour with ratlines, or by right clicking on the via and "Add to net", this will get rid of the errors.

matttay
Posts: 62
Joined: 07 Aug 2010, 18:58

Re: Stiching Layers together with Vias

#3 Post by matttay » 05 May 2016, 03:54

That does the trick, thanks!

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