There is a basic requirement to stitch ground layers together on PCBs, but there seems confusion on the forum. Additionally:
1) The stitch via must survive re-pours (because there are a lot of these vias)
2) Must not generate a DRC error (because there are a lot of these vias)
How can diptrace do this most basic function?
If I place a static via 2 into an area that is ground plane on every layer (tied to the same ground), the default is that I get a DRC error and the via doesn't survive the repour (I get 4 DRC errors per via).
I then specify "hide via ring in layer" which gets rid of two errors. But then resulting via doesn't survive repours.
I then select Thermal Settings-> Use Custom (Whole via, Connect: Yes) and I get a via that survive repours.
But I'm still stuck with a DRC error Copper pour-Drill Gap, where the gap is negative.
How can I make a static via that survive re-pours and doesn't generate a DRC????
Thanks!
Stiching Layers together with Vias
Re: Stiching Layers together with Vias
Try connecting the vias to the pour with ratlines, or by right clicking on the via and "Add to net", this will get rid of the errors.
Re: Stiching Layers together with Vias
That does the trick, thanks!