Trace clearance of GND net against copper pour

Making PCB Layouts, Manual routing, Auto-routing, Copper pouring, Updating from Schematic, Manufacturing Output
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Hansel
Posts: 19
Joined: 09 Jan 2018, 18:39

Trace clearance of GND net against copper pour

#1 Post by Hansel » 27 Jan 2018, 06:04

I want to design a power supply with star-like connections to the LDO's ground pin so as to avoid voltage drops on copper due to high currents. I've experienced hum on my controlled output in the past by just relying solely on copper pour, simply because of currents into the electrolytic capacitors in excess of 10 A during the charge cycle leading to a discernable voltage drop, effectively leading to an audible hum in my audio equipment.

DipTrace has a nice option to keep pads disconnected from copper pour through the settings accessible via "Thermal Settings...". I don't see anything similar for individual traces. I've fiddled with same-net-spacing, class-to-class spacing but can't get it to work. As soon as I update the copper pour, my individual traces merge with the copper pour. I've tried keepouts, but they are hell to create to be perfectly matching with existing traces, simply because there is no way to look at the individual coordinates of trace (at least I haven't found a way) that could use a basis for calculations. It also appears I cannot just simply copy a trace to a different layer and upsize the resulting keepout so as to avoid the copper pour to merge with the trace (at least I haven't found that one either).

Anyone have a suggestion what else I can try? What you see in the picture below shows my ground routing before I update the copper pour. The spacing to the copper pour you see in the picture came through fiddling with keepouts but as you can see, the results turned out poorly.


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Hansel
Posts: 19
Joined: 09 Jan 2018, 18:39

Re: Trace clearance of GND net against copper pour

#2 Post by Hansel » 10 Feb 2018, 08:22

Since no one ever responded, I suppose there's really no elegant solution.

Tomg
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Posts: 1566
Joined: 20 Jun 2015, 14:39

Re: Trace clearance of GND net against copper pour

#3 Post by Tomg » 10 Feb 2018, 09:25

As far as I know, no elegant solution exists.

There have been several requests for some sort of star connection feature, but to date no such tool has materialized. Here is one related discussion that is almost three years old now - viewtopic.php?f=4&t=10376. Inspired by your inquiry, I recently submitted a formal request for a star connection feature that, in my opinion, could be easily-implemented/coded by the developers - viewtopic.php?f=8&t=12061. In the meantime, it looks like we are forced to wrestle with DipTrace's current limitations in this area. The only other way out of this would be to find a PCB design program that supports star connections.

Let's hope Novarm comes up with an elegant solution to this problem soon.
Tom

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