Errors generated by Vias joining a Top and Bottom heatsink plate.

Making PCB Layouts, Manual routing, Auto-routing, Copper pouring, Updating from Schematic, Manufacturing Output
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agareau
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Joined: 16 Mar 2017, 09:21

Errors generated by Vias joining a Top and Bottom heatsink plate.

#1 Post by agareau » 28 Jun 2022, 07:26

I'm sure that I must be doing something wrong, but I can't figure out what.
When I attach a "Top" layer based heatsink plate to a "Bottom" layer heatsink plate,
by using static Vias; I get a small red circle error for each of the Vias,
inspite of attaching to the proper NEts, both "plates". This renders the "Verification"
tool useless due to the "hundreds" of Errors generated. Help !

Tomg
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Re: Errors generated by Vias joining a Top and Bottom heatsink plate.

#2 Post by Tomg » 28 Jun 2022, 08:49

Are the "plates" copper pours? If so, were they updated after adding the vias?
Tom

agareau
Posts: 54
Joined: 16 Mar 2017, 09:21

Re: Errors generated by Vias joining a Top and Bottom heatsink plate.

#3 Post by agareau » 29 Jun 2022, 04:18

No, they are not "copper poured".
They were created with the "drawing tool" and assigned to the different layers.

Tomg
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Re: Errors generated by Vias joining a Top and Bottom heatsink plate.

#4 Post by Tomg » 29 Jun 2022, 09:21

From your description I can assume that the added "plates" are drawing figures assigned to the Signal/Plane layer on both sides of the board. In this case, make sure all of the vias belong to the same net, then do the same for the new Signal/Plane drawing figures. Once that is accomplished, those error flags will disappear.
Tom

agareau
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Joined: 16 Mar 2017, 09:21

Re: Errors generated by Vias joining a Top and Bottom heatsink plate.

#5 Post by agareau » 03 Jul 2022, 02:54

Yes, you are correct. The plates were added to the signal layers; top and bottom.
I did assign all of the vias to the appropiate Net, a rather tedious job.
However, I was unable to assign the plates to the Net. I could not find a command to do so.
Can you explain HOW ?
Also, maybe you can suggest a better or easier way of inserting "Heatsinks".
(And BTW, Hello Tom and as usual, Thank you. It's been a while, Andre)

Tomg
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Re: Errors generated by Vias joining a Top and Bottom heatsink plate.

#6 Post by Tomg » 03 Jul 2022, 08:18

Hi Andre.
1) Right-click on a shape (plate) and select "Properties..." in the context menu to bring up the Shape Properties dialog window.
2) In the Shape Properties dialog window make sure "Type:" is set to "Signal", choose the appropriate net in the "Net:" drop-list and click on the [OK] button.

There is a roundabout way to speed up the process of assigning multiple vias to one net. After the first via has been assigned to the net, enable the "Place Ratline" tool, left-click on the first via and then left-click on the next via. This will place a ratline between the first two vias that will connect the second via to the first via's net. With the "Place Ratline" tool still enabled, connect the second via to the next (third) via the same way. Continue chaining more vias together until all of the desired vias have been connected to the net.
Tom

agareau
Posts: 54
Joined: 16 Mar 2017, 09:21

Re: Errors generated by Vias joining a Top and Bottom heatsink plate.

#7 Post by agareau » 03 Jul 2022, 10:26

Thanks again Tom !
May you enjoy Summer.
Andre

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KevinA
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Joined: 18 Dec 2015, 15:35

Re: Errors generated by Vias joining a Top and Bottom heatsink plate.

#8 Post by KevinA » 05 Jul 2022, 09:58

Not that I encourage adding features before Push & Shove is finally done but:

Copy Matrix
This is a useful function that has never been finished. If I have a Static VIA selected then click Copy Matrix I should get a pop-up window with three check boxes: Style, Net and All

This would give the Copy Matrix function the ability to build an array of vias with only defining the properties of one via instead of manually touching each via.

Tom, another Tomg collectable tip as usual!

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