Silk layer in STEP output

Post your feature requests here. Please use search function to ensure it is not here yet.
Post Reply
Message
Author
LeFish
Posts: 10
Joined: 02 Jun 2016, 08:49

Silk layer in STEP output

#1 Post by LeFish » 14 Nov 2022, 22:32

Hi there,

right now the only way to get the silk screen of the board in the exported 3d model is to export as VRML. VRML (WRL) files are hard to process in most CAD-Systems as they are surface and vertices based rather than volumetric solid body based models.

Sometimes silk screen is important in further processing the pcb.

It would be great if we could export the silk also as part of STEP files.

To circumvent the need of a solid body we could set a small amount of z-height for the silk screen (ideally user-defined as some CAD systems have a coarse resolution filter for imported STEP models) - let's say 0.1 mm by default.

Thanks!

Best regards
LeFish

firatdede
Posts: 13
Joined: 25 Jan 2014, 15:20

Re: Silk layer in STEP output

#2 Post by firatdede » 10 Dec 2022, 08:49

Yes! It would be awesome, we can use 3d outputs at our designs, renders better with silkscreen.

Post Reply