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Re: Copper pour clearance issues

Posted: 27 Nov 2019, 17:49
by kjrowett
Tom - thanks...

A colleague just pointed out there are actually two copper pours, with the boundary right where the error is occurring. Both copper pours are in the same net - GND, and have the same priority. That has to cause the pour fill algorithm some issues. Why did I design the copper pours that way, you would ask? The answer is - I inherited the design, and made ONE change.

KR

Re: Copper pour clearance issues

Posted: 27 Nov 2019, 18:08
by Tomg
KR,
Glad you were able to sort things out.
-Tom

Re: Copper pour clearance issues

Posted: 28 Nov 2019, 10:19
by Alex
Kevin sent PCB file to DipTrace support. There are two touching copper pours on the board. Both copper pours are connected to the same net, both have similar parameters except "Use net clearance" option. That is the reason of DRC errors.