Vias on board but not used

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auto-mation-assist
Posts: 9
Joined: 31 Jan 2021, 17:25

Vias on board but not used

#1 Post by auto-mation-assist » 28 Aug 2021, 18:00

I noticed that running design checks that 4.1.3.1 does not seem to report that there are through drilled vias that are only connected on the top layer. It would be nice if it would report these to help with cleanup work.

Another thing that does not seem right to me is that in the schematic entry it is possible to place wires that are close to making a connection but don't actually make a connection. The only way I found to check for this is to click on the wire and see if the entire net that its supposed to connect to changes color or not. Perhaps adding vertical and horizontal on screen lines that follow mouse position would help in lining up the snap too points.

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KevinA
Posts: 639
Joined: 18 Dec 2015, 08:35

Re: Vias on board but not used

#2 Post by KevinA » 29 Aug 2021, 04:28

On a PCB, Top and Bottom layers with copper pour, remove component that is connected to the bottom layer leaves the via used to connect the SMD. No errors during DRC since the via net is connected to a valid net.
Perhaps an option add: Verification/Design Rules/Options: a check box for orphan via?

When I removed the component I could see the net highlight and the via, I ignored it to get your orphan via, normally I would have removed it with the component.
The Schematic entry issue is a learning curve, we all have been through it, you learn, while thinking about it I realized I couldn't remember that error happening since version 3.0 ...

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