Copper pour clearance issues

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Joined: 15 Apr 2019, 12:53

Re: Copper pour clearance issues

#11 Post by kjrowett » 27 Nov 2019, 17:49

Tom - thanks...

A colleague just pointed out there are actually two copper pours, with the boundary right where the error is occurring. Both copper pours are in the same net - GND, and have the same priority. That has to cause the pour fill algorithm some issues. Why did I design the copper pours that way, you would ask? The answer is - I inherited the design, and made ONE change.


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Joined: 20 Jun 2015, 14:39

Re: Copper pour clearance issues

#12 Post by Tomg » 27 Nov 2019, 18:08

Glad you were able to sort things out.

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Re: Copper pour clearance issues

#13 Post by Alex » 28 Nov 2019, 10:19

Kevin sent PCB file to DipTrace support. There are two touching copper pours on the board. Both copper pours are connected to the same net, both have similar parameters except "Use net clearance" option. That is the reason of DRC errors.

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